Micro-architectural Attacks on RISC-V Devices (available)

Starting Date: Summer '21
Duration: 6 weeks
Time commitment: Full time
Prerequisites: Good programming skills in assembly and C/C++. Any experience with microcontrollers and real-time operating systems will be highly beneficial.

RISC-V is a royalty-free instruction set architecture (ISA) introduced in 2010 with substantial differences to ARM and X86-64 platforms. Its open-source nature threatens to disrupt the status quo of these widely deployed proprietary processor architectures. RISC-V devices have, very recently, started to reach the commercial marketplace. Future potential deployments of such RISC-V devices includes industrial sensing, home automation, automotive infotainment, and other cyber-physical systems.

Despite this, RISC-V platforms remain relatively under-explored from a systems security perspective. In particular, their susceptibility to recent micro-architectural vulnerabilities is not fully characterised, such as Spectre- and Meltdown-type attacks. These attacks exploit side-effects arising from modern CPU features, e.g. speculative and out-of-order (OoO) execution, which remain fruitful vectors for recovering cryptographic keys and other sensitive data.

In this UROP project, the candidate will develop a toolbox of micro-architectural attacks on RISC-V platforms. Leveraging the resources of the ISG’s Smart Card Centre, proof-of-concept attacks will be developed using RISC-V development boards while following security research best practices (e.g. responsible disclosure). A lab report and tutorial information will also be developed for assisting practitioners in the field.

Deliverables

  • A repository of micro-architectural attacks for recovering secret data from RISC-V systems in a controlled environment.
  • A video demonstration and lab report detailing the project’s findings.

ISG-SCC Track Record

The ISG’s Smart Card and IoT Security Centre (ISG-SCC) has successfully run the UROP for the last three years. These years have produced a patent application (under review by patent office), a commercial demo (MVP), and five research papers. Undergraduate students are named as first authors on the papers and co-inventors on any patent applications. Research papers by undergraduate students have won a ‘best student paper award’ and being pivotal for a World Economic Forum’s project for anti-corruption project. The ISG-SCC’s ethos is that undergraduate students have the talent and imagination to sought interesting, unique and innovative solutions. They just need a guiding hand from established researchers, and this is what ISG-SCC will provide during the UROP project.